Statistical analysis and filter design for conducted emission noise

Electromagnetic compatibility (EMC) is the ability of equipment and system to function as intended without degradation or malfunction in their intended operational electromagnetic environment. Further, the equipment or system should not adversely affect the operation of, or be adversely affected by any other equipment. There are two categories of Electromagnetic Compatibility; (1) Electromagnetic Susceptibility (EMS) (2) Electromagnetic Interference (EMI). EMS and EMI can be further divided into two categories namely radiated and conducted. Conducted emission is the unwanted currents that are produced by electronic and electrical equipments emitted through the power lines. The main sources of conducted emission are common mode current and differential mode current. These currents will interfere with any equipments that are connected to the same power lines. EMC standards pertaining to the conducted emission (such as EN55014) define the limit lines that should not be exceeded or the product cannot be marketed. In order to avoid non-compliance to the standards, most electronic/electrical equipments have power line filter installed into them. However, these filters are not effective enough because they were designed without considering the emission currents characteristics. This project proposed a method to improve the design of a power line filter by analyzing the characteristic of the emission current noise. The results from the statistical measurements can be used to identify the range of frequencies where most of the noises are located. Eighty four blenders were used as a sample to identify the characteristic of the noise. It was found out that the conducted emission exceed the limit line from 150kHz to 1MHz by 5dB and by lOdB at frequencies from 1MHz to 30MHz. A butterworth filter with cut-off frequency of 70.56kHz and bandwidth from 0 to 120kHz was designed. The parameters of the filter were based on the statistical data of the conducted emission. The test result shows that the filter attenuate the noise about 42dB at frequency range of 150kHz to 10MHz and lOdB at frequency range from 10MHz to 30MHz. The low attenuation at frequencies from 10MHz to 30MHz is due to the existence of capacitive and skin effect. A better filter can be achieved if a higher quality component is used in the fabrication

A study on ultra-low power and large-scale design of digital circuit for wireless communications

The continuous growth of recent mobile and portable devices has caused a push greater towards low-power circuit designs. Various methods and techniques have been found, for example, the utilization of concurrent or pipeline architecture with low supply voltage for traditional circuits. Proper designs of subthreshold circuits operating in a weak inversion region achieves ultra-low threshold and supply voltages and has been studied for both analog and digital circuits. The analog circuit has been studied and implemented in many areas such as speech signal and image processing. On the other hand, digital circuits have been studied for very low clock frequency and can be applied in medical devices such as pacemakers and defibrillators. For the idle state of low-power, subthreshold voltage condition has been used for microprocessors in ultra-low voltage operation and leakage current. The idea to study subthreshold operation comes after much research carried out through conventional analysis focusing on, for example, low power, low voltage, low frequency, and application in small circuit systems. Recently, as a result of the aggressive scaling of transistor size for high-performance applications, not only does subthreshold leakage current increase exponentially, but gate leakage and reverse-biased source-substrate and drain-substrate junction band-to-band tunneling (BTBT) currents also increase significantly. The tunneling currents are detrimental to the functionality of the devices. The well-known methods of low-power design (such as voltage scaling, switching activity reduction, architectural techniques of pipelining and parallelism, computer-aided design (CAD) techniques of device sizing, interconnect, and logic optimization). This may not be sufficient in many applications such as portable computing gadgets, and medical electronics, where ultra-low power consumption with medium frequency of operation is the primary requirement. To cope with this, several novel design techniques have been proposed. Energy recovery or adiabatic techniques are promising for reducing power in computation by orders of magnitude. However, they involve the use of high-quality inductors, which makes integration difficult. More recently, the design of digital subthreshold logic was investigated with transistors operated in the subthreshold region. The aim of this study is to achieve ultra-low power communication circuits operating at high frequency. In this situation, we focus on implementing large-scale subthreshold circuits and must explore a new design in which only the CMOS standard cell library is used and simplify the modeling procedure of subthreshold circuits. The conventional design involves subthreshold analysis on a transistor level or cell library preparation under multiple voltage conditions. This procedure has disadvantageous that requires a long time to estimate the circuit performance for operation in the subthreshold region. We proposed scale modeling so we need only to use a typical cell library, which is suitable for large-scale digital circuits such as wireless communication circuits. In the proposed method, each CMOS logic cell operating in the subthreshold region in circuit delays and power dissipation are analyzed and scaled factors are obtained by mapping from typical to subthreshold voltage conditions. This process does not need preparation of a special-purpose CMOS library operating in the sub-threshold region. The critical path delay is also obtained by scaling factors and used for determining the optimal voltage condition that satisfies the required timing constrains. For practical examples, we have designed wireless clrcuits of a channel equalizer, FIR filter and FlT used in an OFDM receiver. These circuits have been power dissipated by adjusting the overall voltage conditions to satisfy the required timing constrains of IEEE802.11a standard. Continuing from the first research, we explore the power reduction on dynamic wordlength and voltage scaling for digital signal processing circuits. The determination of wordlength in digital signal processing (DSP) affects system performance, hardware size, and power consumption. A large wordlength yields better performance in digital hardware but increases power consumption. A small wordlength degrades system performance if the dynamic range is insufficient. Use of a fixed wordlength determined in design-level lacks flexibility for such changeable environments. Use of a dynamic variable wordlength technique can maintain system performance and keep power consumption low by dynamically changing an optimal wordlength for various environments. This technique has been applied to an OFDM demodulator and to an equalizer. There are two ways in reducing power for variable wordlength. One is to decrease switching activities by stopping unnecessary bit operations. Variable wordlength chooses small and large wordlength modes. For a small wordlength mode, unused bits can be masked by zero values. Gated clocks are effective in halting switching activities for registers. However, it requires a clock management in its system. The other is voltage scaling (called as minimum power locus) to normalize a circuit delay for each wordlength mode. A small wordlength has a timing margin in a critical path when the timing delay of a large wordlength is adopted. It enables decreasing a voltage so as to have the same circuit delay of a large wordlength. Thus, dynamic wordlength and voltage scaling (DWVS) is suitable for power reduction in variable wordlength architecture. This second research focus is power modeling for DWVS. The work does transistor-level simulation or actual measurements to analyze power consumption of variable wordlength. However, more rapid analysis and estimation done at gate-level and function-level are required for large scale circuits. We present a new power modeling approach where both voltage scaling and switching activities are modeled as DWVS parameters

Quantum-dot Cellular Automata: Review Paper

Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS.  Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl

Full adder circuit design with novel lower complexity XOR gate in QCA technology

Quantum-dot Cellular Automata (QCA) is a new technology for designing digital circuits in Nanoscale. This technology utilizes quantum dots rather than diodes and transistors. QCA supplies a new computation platform, where binary data can be represented by polarized cells, which can defne by the electron’s confgurations inside the cell. This paper explains QCA based combinational circuit design; such as half-adder and full-adder, by only one uniform layer of cells. The proposed design is accomplished using a novel XOR gate. The proposed XOR gate has a 50% speed improvement and 35% reduction in the number of cells needed over the best reported XOR. The results of QCADesigner software show that the proposed designs have less complexity and less power consumption than previous designs

Design of Power-Efficient Structures of the CAM Cell using a New Approach in QCA Nanoelectronics Technology

Quantum-dot Cellular Automata (QCA) is a new emerging nano-electronic technology. Owing to its many fa-vorable features such as low energy requirements, high speed, and small size, QCA is being actively suggested as a future CMOS replacement by researchers. Many digital circuits have been introduced in QCA technology, most of them aiming to reach the function with optimum construction in terms of area, cell count and power consumption. The memory circuit is the main building block in the digital system therefore the researchers paid attention to design the memory cells with minimum requirements. In this paper, a new methodology is intro-duced to design two forms of CAM cell. The proposed designs required two 2:1 multiplexers, one OR gate and one inverter. The first proposed design reduces the power consumption by 53.3%, 35% and 25.9% at (0.5 Ek, 1 Ek, and 1.5 Ek) while the second design by 53.2%, 31.9% and 20.5% (0.5 Ek, 1 Ek, and 1.5 Ek) respectively

A content-addressable memory structure using novel majority gate with 5-input in quantum-dot cellular automata

Quantum-dot Cellular Automata (QCA) technology is one of the most important new nanotechnologies and is a suitable replacement for CMOS circuits. Majority gate and Inverter are the primary building blocks in QCA circuits. Content Addressable Memory (CAM) is a type of memory used in applications that require high speed. In this paper, a novel five input majority gate is introduced. This gate is simulated with QCADesigner tool and compared with previous same structures. Then, the proposed gate used to design a CAM cell in a single layer after deriving the minority gate from the proposed majority gate. The proposed CAM cell has a simple and robust structure and does not require wire crossover, also it reduces circuit complexity by 7% in term of cell count compared to existing structures

Soil moisture monitoring using field programmable gate array

This paper presents a solution for remote monitoring and sensing of different agricultural parameters that effect the plant growth and productivity. Hardware descriptive language has been used for the implementation of proposed topology on Field Programmable Gate Arrays. The hardware used for this purpose is an Altera board. The simulated results take into consideration the environmental factors such as the humidity, soil moisture content and the temperature. The proposed system continuously monitors the environmental changes for any updates. The system also controls a water motor that is turned on as the system senses the reduction in moisture content. The system implementation on hard wave level show promising results and have been discussed in detailed

Soil moisture monitoring using field programmable gate array

This paper presents a solution for remote monitoring and sensing of different agricultural parameters that effect the plant growth and productivity. Hardware descriptive language has been used for the implementation of proposed topology on Field Programmable Gate Arrays. The hardware used for this purpose is an Altera board. The simulated results take into consideration the environmental factors such as the humidity, soil moisture content and the temperature. The proposed system continuously monitors the environmental changes for any updates. The system also controls a water motor that is turned on as the system senses the reduction in moisture content. The system implementation on hard wave level show promising results and have been discussed in detailed